1. Field of the Invention
The present invention relates in general to electronic devices and specifically to a fully programmable phase locked loop.
2. Description of the Related Art
Phase locked loops (PLLs) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal maybe at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal.
A typical PLL includes a phase frequency detector (PFD), a charge pump, and a voltage controlled oscillator (VCO), among other supporting circuitry. The PFD compares an input or system clock with an output clock and provides clock control signals to the charge pump. The charge pump adds or subtracts charge to a filter capacitor based on the clock control signals and generates a control voltage that controls the frequency of the VCO. Another block may be provided to buffer and divide or multiply the output clock, which is fed back to the PFD for comparison with the system clock.
The conventional PLL architecture is not ideal for newer process technologies, does not scale well from one process technology to the next, and must be redesigned for use in various electronic devices in different markets. The drive to reduce the size of electronic devices has increased the difficulty of implementing capacitors in a semiconductor device. In particular, reducing the thickness of gate oxides increases the gate leakage currents of semiconductor capacitor devices. Also, reducing the size of semiconductor devices means that a proportionally larger area of the device must be allocated to obtain the same capacitance, unless the thickness of the insulator is reduced. Reducing the thickness of the insulator, however, increases the leakage currents of the semiconductor capacitor devices.
The transistors implemented using advanced CMOS processes, such as 90-nm (nanometer) CMOS, are exhibiting non-ideal behavioral traits for implementation of critical analog functions, such as current and voltage sources or references, VCO's, charge pumps, etc. Some of these non-ideal transistor traits include increased gate tunneling current, increased drain-source leakage, reduced voltage headroom due to VDD scaling, and increased noise susceptibility due to decreased threshold voltages. Furthermore, with respect to PLL design, the very high gain VCOs are causing increased cycle-to-cycle jitter, coupled with increased phase drift due to the ever increasing discrepancy between the internal speed of the processor and the interface reference clock speeds. Modern processors, for example, typically operate in the gigahertz (GHz) range whereas the interface reference clock speeds typically operate in the 16–166 megahertz (MHz) range. Fully digital PLLs can alleviate some of the issues but do not scale very well. Furthermore, the need to integrate more PLLs on chip for System-On-Chip (SOC) applications forces more unique PLL implementations which cause design overhead and risk.
A receiver or level shifter is used at the front end of the PLL to interface with clocks that may be generated at different voltage levels. The clocks oscillate at different voltage levels and with different slopes on the rising and falling edges, and thus are difficult to match for de-skew control. Older process technologies were designed for higher voltages, such as 1.5 Volts (V), 18.V, 2.5V, 3.3V, etc., whereas newer technologies are designed for use with lower voltage levels, such as on the order of 1–1.2V. Dual-Gate Oxide (DGO) or “thick-gate” transistors are used to withstand the higher voltage levels, but do not operate well at the lower voltage levels. Single-Gate Oxide (SGO) or “thin-gate” transistors are smaller and faster and optimized for low voltage operation, but are unable to handle the higher voltage levels. In other configurations, the faster path using thin-gate devices was interfaced to higher voltage devices for delay matching with the higher voltage reference or system clock, effectively slowing down the front end interface. Also, such interface to higher voltage devices was a less than optimal solution that complicated skew control and that was difficult to optimize when the PLL was required to operate over a wide range of supply voltage.
It is desired to provide a single programmable PLL that is scalable across design technologies, that addresses multiple market needs, that provides multi-bandwidth and phase control, and that provides complete control of the damping coefficient and natural frequency of the PLL. For example, it is desired to provide a programmable PLL front end to interface a reference clock at any of a variety of voltage levels without slowing down either clock. More particularly, it is desired to match the levels of and to provide de-skew control between the reference and feedback clocks without slowing down either path. Furthermore, it is desired to provide a VCO with dynamically adjusted phase control that does not use traditional resistor or current source devices and that does not rely on the accurate resistor, capacitor or transistor absolute values.